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br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 1/25 1024 8 bit electrically erasable prom br24l08-w / br24l08f-w / br24l08fj-w / br24l08fv-w / br24l08fvm-w the br24l08-w series is 2-wire (i 2 c bus type) serial eeproms which are electrically programmable. ? i 2 c bus is a registered trademark of philips. z applications general purpose z features 1) 1024 registers 8 bits serial architecture. 2) single power supply (1.8v to 5.5v). 3) two wire serial interface. 4) self-timed write cycle with automatic erase. 5) 16byte page write mode. 6) low power consumption. write (5v) : 1.5ma (typ.) read (5v) : 0.2ma (typ.) standby (5v) : 0.1 a (typ.) 7) data security write protect feature (wp pin). inhibit to write at low v cc . 8) small package - - - dip8 / so p8 / sop-j8 / ssop-b8 / msop-8 9) high reliability eeprom with double-cell structure. 10) high reliability fine pattern cmos technology. 11) endurance : 1,000,000 erase / write cycles 12) data retention : 40 years 13) filtered inputs in scl ? sda for noise suppression. 14) initial data ffh in all address. z absolute maximum ratings (ta=25 c) parameter symbol limits unit supply voltage ? 0.3 to + 6.5 v power dissipation mw storage temperature ? 65 to + 125 c operating temperature c terminal voltage ? v ? 40 to + 85 v cc ? 0.3 to v cc + 0.3 pd tstg topr ? 1 450(sop-j8) 450(sop8) 800(dip8) ? 2 ? 2 ? 3 ? 4 300(ssop-b8) ? 1 reduced by 8.0mw for each increase in ta of 1 c over 25 c. ? 2 reduced by 4.5mw for each increase in ta of 1 c over 25 c. ? 3 reduced by 3.0mw for each increase in ta of 1 c over 25 c. ? 4 reduced by 3.1mw for each increase in ta of 1 c over 25 c. 310(msop8)
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 2/25 z recommended operating conditions (ta=25 c) parameter symbol limits unit supply voltage v input voltage v in v v cc 0 to v cc 1.8 to 5.5 z dc operating characteristics (unless otherwise specified ta =? 40 to 85 c, v cc = 1.8 to 5.5v) parameter symbol min. typ. max. unit conditions v ih1 ?? v v il1 ?? 0.3v cc v v ol2 ?? 0.2 v input leakage current i li ? 1 a v in = 0v to v cc output leakage current i lo ? 1 ? 1 ? 1 a operating current i cc2 ? 0.5 ma standby current i sb ? ? i cc1 ? 2.0 ma ? ? 2.0 a 0.7v cc 2.5v v cc 5.5v 2.5v v cc 5.5v i ol = 0.7ma, 1.8v v cc 5.5v, (sda) v cc = 5.5v, f scl = 400khz random read, current read, sequential read v out = 0v to v cc "high" input volatge 1 "low" input volatge 1 v ih2 ?? v v il2 ?? 0.2v cc v 0.8v cc 1.8v v cc < 2.5v 1.8v v cc < 2.5v "high" input volatge 2 "low" input volatge 2 v ol1 ?? 0.4 v i ol = 3.0ma, 2.5v v cc 5.5v, (sda) "low" output volatge 2 "low" output volatge 1 v cc = 5.5v, sda ? scl = v cc , a0, a1, a2=gnd, wp=gnd v cc = 5.5v, f scl = 400khz, t wr =5ms, byte write, page write this product is not designed for protection against radioactive rays.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 3/25 z dimension fig.1(a) physical dimension (units : mm) dip8 (br24l08-w) 0.5 0.1 3.2 0.2 3.4 0.3 85 14 9.3 0.3 6.5 0.3 0.3 0.1 0.51min. 2.54 0 ~ 15 7.62 0.3min. 0.15 0.1 0.4 0.1 0.11 6.2 0.3 4.4 0.2 5.0 0.2 85 4 1 1.27 1.5 0.1 0.1 fig.1(b) physical dimension (units : mm) sop8 (br24l08f-w) fig.1(c) physical dimension (units : mm) sop-j8 (br24l08fj-w) 0.1 0.45min. 0.42 0.1 4.9 0.2 85 4 123 1.27 76 0.2 0.1 0.175 6.0 0.3 3.9 0.2 1.375 0.1 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 fig.1(d) physical dimension (units : mm) ssop-b8 (br24l08fv-w) fig.1(e) physical dimension (units : mm) msop8 (br24l08fvm-w) 4 1 5 8 2.9 0.1 0.475 0.65 4.0 0.2 0.6 0.2 0.29 0.15 2.8 0.1 0.75 0.05 0.08 0.05 0.9max. 0.08 s 0.08 m 0.145 + 0.05 ? 0.03 0.22 + 0.05 ? 0.04
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 4/25 z block diagram 1 a0 a1 2 a2 3 gnd 4 v cc 8 wp 7 6 scl sda 5 32kbit eeprom array control logic high voltage generator vcc level detect 10bit 8bit ack stop start address decoder slave word address register 10bit data register fig.2 block diagram z pin configuration br24l08-w br24l08f-w br24l08fj-w br24l08fv-w br24l08fvm-w v cc a0 wp a1 scl a2 sda gnd 1234 5 6 7 8 fig.3 pin layout z pin name write protect input power supply function ground (0v) slave address set serial clock input sda v cc a2 pin name gnd wp scl i / o ? ? in out of use a0, a1 ? in in in / out slave and word address, serial data input, serial data output ? 1 an open drain output requires a pull-up resistor. ? 1
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 5/25 z ac operating characteristics (unless otherwise specified ta =? 40 to 85 c, v cc = 1.8 to 5.5v) parameter symbol fast-mode 2.5v vcc 5.5v standard-mode 1.8v vcc 5.5v unit fscl khz thigh noise spike width (sda and scl) twr tl ms data clock "high" period clock frequency s data clock "low" period tlow s sda and scl rise time ? 1 ? 1 ? 1 not 100% tested. tr s sda and scl fall time tf s start condition hold time thd:sta s start condition setup time tsu:sta s input data hold time thd:dat ns input data setup time tsu:dat ns output data delay time output data hold time tpd s stop condition setup time tdh s bus free time tsu:sto s tbuf min. ? 0.6 ? ? 1.2 ? ? 0.6 0.6 0 100 0.1 0.1 0.6 1.2 typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 400 ? 5 ? 0.3 0.3 ? ? ? ? 0.9 ? ? ? min. ? 4.0 ? ? 4.7 ? ? 4.0 4.7 0 250 0.2 0.2 4.7 4.7 typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 100 ? tsu:wp wp high period s 0.1 ?? 0.1 ?? 5 0.1 ? 1.0 0.3 ? ? ? ? 3.5 wp setup time thd:wp ns s 0 ? ? 0.1 0 ? ? ? ? ? s write cycle time wp hold time thigh:wp s 1.0 ?? 1.0 ??
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 6/25 z synchronous data timing t buf t pd t high t hd : sta t low t f t r scl start bit stop bit scl sda t dh t su : dat t hd : dat t su : sto t hd : sta t su : sta sda (out) sda (in) fig.4 synchronous data timing ? sda data is latched into the chip at the rising edge of scl clock. ? output data toggles at the falling edge of scl clock. z write cycle timing ack d0 t wr sda scl start condition stop condition write data (n) fig.5 write cycle timing
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 7/25 z wp timing scl sda wp t hd : wp t wr stop bit ack ack d1 data (n) data (1) t su : wp d0 fig.6(a) wp timing of the write operation scl sda wp ack ack d1 data (n) data (1) t high : wp d0 fig.6(b) wp timing of the write cancel operation ? for the write operation, wp must be ?low? during the period of time from the rising edge of the clock which takes in d0 of first byte until the end of t wr . ( see fig.6 (a) ) during this period, write operation is canceled by setting wp ?high?. ( see fig.6 (b) ) ? in the case of setting wp ?high? during t wr , write operation is stopped in the middle and the data of accessing address is not guaranteed. please write correct data again in the case.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 8/25 z device operation 1) start condition (recognition of start bit) ? all commands are proceeded by the start condition, which is a high to low transition of sda when scl is high. ? the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. (see fig.4 synchronous data timing) 2) stop condition (recognition of stop bit) ? all communications must be terminated by a stop condition, which is a low to high transition of sda when scl is high. (see fig.4 synchronous data timing) 3) notice about write command ? in the case that stop condition is not executed in write mode, transferred data will not be written in a memory. 4) device addressing ? following a start condition, the master output the slave address to be accessed. ? the most significant four bits of the slave address are the ?d evice type identifier?, for this device it is fixed as ?1010?. ? the next bit (device address) identify the specified device on the bus. the device address is defined by the state of a2 input pin. this ic works only when the device address inputted from sda pin correspond to the state of a2 input pin. using this address scheme, up to two devices may be connected to the bus. ? the next two bits (p1, p0) are used by the master to select t four 256 word page of memory. p1, p0 set to ?0? ?0? - - - - - - 1page (000 to 0ff) p1, p0 set to ?0? ?1? - - - - - - 2page (100 to 1ff) p1, p0 set to ?1? ?0? - - - - - - 3page (200 to 2ff) p1, p0 set to ?1? ?1? - - - - - - 4page (300 to 3ff) ? the last bit of the stream (r/w - - - read / write) determines the operation to be performed. when set to ?1?, a read operation is selected ; when set to ?0?, a write operation is selected. r / w set to ?0? - - - - - - write (i ncluding word address input of random read) r / w set to ?1? - - - - - - read a2 p1 p0 1010 r / w 5) write protect (wp) when wp pin set to v cc (h level), write protect is set for 1024 words (all address). when wp pin set to gnd (l level), enable to write 1024 words (all address). either control this pin or connect to gnd (or v cc ). it is inhibited from being left unconnected.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 9/25 6) acknowledge ? acknowledge is a software convention used to indicate successful data transfers. the transmitter device will release the bus after transmitting eight bits. (when inputting the slave address in the write or read operation, transmitter is -com. when outputti ng the data in the read operation, it is this device.) ? during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that the eight bits of data has been received. (when inputting the slave address in the write or read operation, receiver is this device. when outputting the data in the read operation, it is -com.) ? the device will respond with an acknowledge after recognition of a start condition and its slave address (8bit). ? in the write mode, the device will respond with an ack nowledge, after the receipt of each subsequent 8-bit word (word address and write data). ? in the read mode, the device will transmit eight bit of data, release the sda line, and monitor the line for an acknowledge. ? if an acknowledge is detected, and no stop condition is generated by the master, the device will continue to transmit the data. if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby m ode. (see fig.7 acknowledge response from receiver) 189 scl sda sda start condition (start bit) acknowledge signal (ack signal) (from ? com) output data) ( ? com (ic output data) fig.7 acknowledge response from receiver
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 10/25 z byte write sda line wp s t a r t slave address 10 0 1 r / w w r i t e a c k a c k d7 data d0 s t o p fig.8 byte write cycle timing a c k word address wa 0 wa 7 p0 p1 a2 ? by using this command, the data is programmed into the indicated word address. ? when the master generates a stop condition, the device begins the internal write cycle to the nonvolatile memory array. z page write fig.9 page write cycle timing sda line wp slave address 10 0 1 r / w a c k a c k a c k d7 data (n) d0 data (n + 15) d0 word address (n) a c k wa 0 wa 7 p0 p1 a2 s t a r t w r i t e s t o p ? this device is capable of sixteen byte page write operation. ? when two or more byte data are inputted, the four low order address bits are internally incremented by one after the receipt of each word. the six higher order bits of the address (p1, p0, wa7 to wa4) remain constant. ? if the master transmits more than sixteen words, prior to generating the stop condition, the address counter will ?roll over?, and the previous transmitted data will be overwritten.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 11/25 z current read sda line s t a r t slave address 11 r / w a c k a c k data s t o p 00 a2 p1 p0 d7 d0 r e a d fig.10 current read cycle timing ? in case that the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). thus current read outputs the data of the next word address (n + 1). if the last command is byte or page write, the internal address counter stays at the last address (n). thus current read outputs the data of the word address (n). ? if an acknowledge is detected, and no stop condition is generated by the master ( -com), the device will continue to transmit the data. [ it can transmit all data (8kbit 1024word) ] ? if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode. note) if an acknowledge is detected with ?low? level, not ?high? level, command will become sequential read. so the device transmits the next data, read is not terminated . in the case of terminating read, input acknowledge with ?high? always, then input stop condition. z random read slave address sda line s t a r t 11 0 0 a2 p1 p0 a2a1ps r / w w r i t e fig.11 random read cycle timing s t o p a c k r e a d data(n) slave address s t a r t r / w a c k 11 0 0 d7 d0 wa 0 wa 7 word address(n) a c k a c k ? random read operation allows the master to access any memory location indicated word address. ? if an acknowledge is detected, and no stop condition is generated by the master ( -com), the device will continue to transmit the data. [ it can transmit all data (8kbit 1024word) ] ? if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode. note) if an acknowledge is detected with ?low? level, not ?high? level, command will become sequential read. so the device transmits the next data, read is not terminated . in the case of terminating read, input acknowledge with ?high? always, then input stop condition.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 12/25 z sequential read s t a r t slave address r / w a c k a c k a c k a c k r e a d data(n) data(n + x) sda line 11 00a2 p1 p0 d7 d7 d0 d0 s t o p fig.12 sequential read cycle timing (current read) ? if an acknowledge is detected, and no stop condition is generated by the master ( -com), the device will continue to transmit the data. [ it can transmit all data (8kbit 1024word) ] ? if an acknowledge is not detected, the device will terminate further data transmissions and await a stop condition before returning to the standby mode. ? the sequential read operation can be performed with both current read and random read. note) if an acknowledge is detected with ?low? level, not ?high? level, command will become sequential read. so the device transmits the next data, read is not terminated . in the case of terminating read, input acknowledge with ?high? always, then input stop condition.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 13/25 z application 1) wp effective timing wp is fixed to ?h? or ?l? usually. but in case of controlling wp to cancel the write command, please pay attention to [ wp effective timing ] as follows. during write command input, write command is canceled by controlling wp ?h? within the wp cancellation effective period. the period from the start condition to the rising edge of t he clock which take in d0 of the data (the first byte of the data for page write) is the cancellation invalid period. wp input is don?t care during the period. setup time for rising edge of the scl which takes in d0 must be more than 100ns. the period from the rising edge of scl which takes in d0 to the end of internal write cycle (t wr ) is the cancellation effective period. in case of setting wp to ?h? during t wr , write operation is stopped in the middle and the data of accessing address is not guaranteed, so that write correct data again please. it is not necessary waiting t wr (5msmax.) after stopping command by wp, because the device is stand by state. s t a r t a c k l a c k l a c k l a c k l a c k l s t o p slave address word address data d7 d6 d5 d4 d3 d2 d1 d0 sda wp twr wp cancellation invalid period wp cancellation effective period no data will be written stop of the write operation data is not guaranteed scl sda d1 d0 ack an enlargement the rising edge of the clock which take in d0 scl sda d0 ack an enlargement the rising edge of sda fig.13 wp effective timing
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 14/25 2) software reset please execute software reset in case that the device is an unexpected state after power up and / or the command input need to be reset. there are some kinds of software reset. here we show three types of example as follows. during dummy clock, please release sda bus (tied to v cc by pull up resistor). during that time, the device may pull the sda line low for acknowledge or outputting or read data. if the master controls the sda line high, it will conflict with the device output low then it makes a current overload. it may cause instantaneous power down and may damage the device. fig.14-(a) dummy clock 14 + start + start command command 12 14 13 sda dummy clock 14 start 2 scl fig.14-(b) start + dummy clock 9 + start command command 12 89 scl sda dummy clock 9 start start fig.14-(c) start 9 command command 123 789 scl sda start 9 ? command starts with start condition.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 15/25 3) acknowledge polling since the device ignore all input commands during the internal write cycle, no ack will be returned. when the master send the next command after the write command, if the device returns the ack, it means that the program is completed. if no ack id returned, it means that the device is still busy. by using acknowledge polling, the waiting time is minimized less than t wr = 5ms. in case of operating write or current read right after write, first, send the slave address (r / w is ?high? or ?low? respectively). after the device returns the ack, continue word address input or data output respectively. s t a r t s t a r t s t a r t s t a r t s t a r t a c k h a c k l a c k l a c k l a c k h a c k h s t o p s t o p write command slave address slave address slave address slave address word address data t wr t wr fig.15 successive write operation by acknowledge polling during the internal write cycle, no ack will be returned. (ack = high) after the internal write cycle is completed ack will be returned (ack = low). then input next word address and data. the first write command the second write command ? ? ? ? ? ?
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 16/25 4) command cancellation by start and stop condition during a command input, it is canceled by the successive inputs of start condition and stop condition. (fig.4) but during ack or data output, the device may output the sda line low. in such cases, operation of start and stop condition is impossible, so that the reset can?t work. execute the software reset in the cases. (see page14) operating the command cancel by start and stop condition during the command of random read or sequential read or current read, internal address counter is not confirmed. therefore operation of current read after this in not valid. operate a random read in this case. fig.16 command cancellation by start and stop condition during the input of slave address 11 00 scl sda start condition stop condition
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 17/25 5) notes for power supply v cc rises through the low voltage region in which internal circuit of ic and the controller are unstable, so that device may not work properly due to an incomplete reset of internal circuit. to prevent this, the device has the f eature of p.o.r. and lv cc . in the case of power up, ke ep the following conditions to ensure functions of p.o.r and lv cc . (1) it is necessary to be ?sda = ?h? ? and ?scl = ?l? or ?h? ?. (2) follow the recommended conditions of t r , t off , vbot for the function of p.o.r. durning power up. t r t off vbot v cc rising wave from v cc 0 recommended conditions of t r , t off , vbot below 10ms t r t off vbot below 100ms below 0.3v below 0.2v above 10ms above 10ms (3) prevent sda and scl from being ?hi-z?. in case that condition 1. and / or 2. cannot be met, take following actions. a) unable to keep condition 1. (s da is ?low? during power up.) control sda, scl to be ?high? as figure below. t low t dh t su:dat after v cc becomes stable sda scl v cc a) scl = "h" and sda = "l" t su:dat after v cc becomes stable b) scl = "l" and sda = "l" b) unable to keep condition 2. after power becomes stable, execute software reset. (see page14 ) c) unable to keep condition 1 and 2. follow the instruction a first, then the instruction b. ? lv cc circuit lv cc circuit inhibit write operation at low voltage, and prevent an inadvertent write. below the lv cc voltage (typ. = 1.2v), write operation is inhibited.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 18/25 6) i / o circuit ? pull up resister of sda pin the pull up resister is needed because sda is nmos open drain. decide the value of this resister (r pu ) properly, by considering v il , i l characteristics of a controller which control the device and v oh , i ol characteristics of the device. if large r pu is chosen, clock frequency need to be slow. in case of small r pu , the operating current increases. ? maximum of r pu maximum of r pu is determined by following factor. c sda rise time determined by r pu and the capacitance of bus line (cbus) must be less than t r . and the other timing must keep the conditions of ac spec. d when sda bus is high, the voltage a of sda bus determined by a total input leak (i l ) of the all devices connected to the bus and r pu must be enough higher than input high level of a controller and the device, including noise margin 0.2v cc . a il il micro computer br24lxx sda pin r pu the capacitance of bus line (cbus) v cc ? i l r pu ? 0.2v cc v ih r pu 0.8v cc ? v ih il r pu 0.8 3 ? 0.7 3 10 10 ? 6 300 [k ? ] examples : when v cc = 3v i l = 10 a v ih = 0.7v cc according to 2
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 19/25 ? the minimum value r pu the minimum value of r pu is determined by following factors. c meet the condition that v olmax = 0.4v, i olmax = 3ma when the device output low on sda line. r pu v cc ? v ol i ol i ol v cc ? v ol r pu d v olmax ( = 0.4v) must be lower than the input low level of the controller and the eeprom including recommended noise margin (0.1v cc ). v olmax v il ? 0.1v cc r pu 3 ? 0.4 3 10 ? 3 867 [ ? ] examples : v cc = 3v, v ol = 0.4v, i ol = 3ma, the v il of the controller and the eeprom is v il = 0.3v cc according to and so that condition is met 1 2 v ol v il = 0.4[v] = 0.3 3 = 0.9[v] ? pull up resister of scl pin in the case that scl is controlled by cmos ou tput, the pull up resister of scl is not needed. but in the case that there is a timi ng at which scl is hi-z, connect scl to v cc with pull up resister. several several dozen k ? is recommended as a pull up resister, which is considered with the driving ability of the output port of the controller. 7) connections of a0, a1, a2, wp pin ? connections of device address pin (a0, a1, a2) the state of device address pin are compared with the device address send by the master, then one of the devices which are connected to the identical bus is selected. pull up or down these pins, or connect them to v cc or gnd. pins which is not used as device address (n.c. pin) may be either high, low, and hi-z. the type of the device which have n.c. pi n br24l16 / f / fj / fv / fvm-w a0, a1, a2 br24l08 / f / fj / fv / fvm-w a0, a1 br24l04 / f / fj / fv / fvm-w a0 ? connections of wp pin the wp input allows or inhibits write operations. when wp is high, only read is available and write to any address is inhibited. both read and write are available when wp is low. in the case that the device is used as a rom, it is recommended that wp is pulled up or connected to v cc . in the case that both read and write are operated, wp pin must be pulled down or connected to gnd or controlled.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 20/25 8) notes for noise on v cc ? about bypass capacitor noise and surges on power line may cause the abnormal function. it is recommended that the bypass capacitors (0.1 f) are attached on the v cc and gnd line beside the device. the attachment of bypass capacitors on the board near by connector is also recommended. gnd v cc print base ic capacitor 0.01 to 0.1 f capacitor 10 to 100 f 9) the notice about the connection of controller ? about r s the open drain interface is recommended for sda port in i 2 c bus. but, in the case that tri-state cmos interface is applied to sda, insert a series resister r s between sda pin of the device and a pull up resister r pu . it limits the current from pmos of controller to nmos of eeprom. r s also protects sda pin from surges. therefore, r s is able to be used though sda port is open drain. sda pin r pu r s controller eeprom "h" output of controller "l" output of eeprom ack scl sda the "h" output of controller and the "l" output of eeprom may cause current overload to sda line.
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 21/25 ? the maximum value of r s the maximum value of r s is determined by following factors. c sda rise time determined by r pu and the capacitance of bus line (cbus ) of sda must be less than t r . and the other timing must also keep the conditions of the ac timing. d when the device outputs low on sda line, the voltage of the bus a determined by r pu and r s must be lower than the inputs low level of the controller, including recommended noise margin (0.1v cc ). v ol v il r pu v cc r s controller eeprom a capacitance of bus line (cbus) r s r pu v il ? v ol ? 0.1v cc 1.1v cc ? v il r s 20 10 3 0.3 3 ? 0.4 ? 0.1 3 1.1 3 ? 0.3 3 + v ol + 0.1v cc v il (v cc ? v ol ) r s r pu + r s 1.67 [k ? ] examples : when v cc = 3v, v il = 0.3v cc , v ol = 0.4v, r pu = 20k ? according to 2 ? the minimum value of r s the minimum value of r s is determined by the current overload due to the conflict on the bus. the current overload may cause noise on the power line and instantaneous power down. the following conditions must be met, where is the maximum permissible current. the maximum permissible current depends on v cc line impedance and so on. it need to be less than 10ma for eeprom. r s v cc r s 3 10 10 ? 3 v cc r s 300 [ ? ] examples : when v cc = 3v, = 10ma r pu r s controller eeprom "l" output "h" output maximum current
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 22/25 10) the special character data the following characteristic data are typ. value. 2 6 5 4 3 2 1 0 01 34 6 5 h input voltage : v ih (v) fig.17 high input voltage v ih (a0,a1,a2,scl,sda,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 6 5 4 3 2 1 0 01 34 6 5 l input voltage : v il (v) fig.18 low input voltage v il (a2,scl,sda,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 1 0.8 0.6 0.4 0.2 0 01 34 6 5 l output voltage : v ol (v) fig.19 low output voltage v ol ? i ol (v cc = 1.8v) l output current : i ol (ma) spec ta = 85 c ta = 25 c ta =? 40 c 2 1 0.8 0.6 0.4 0.2 0 01 34 6 5 l output voltage : v ol (v) fig.20 low output voltage v ol ? i ol (v cc = 2.5v) l output current : i ol (ma) spec ta = 85 c ta = 25 c ta =? 40 c 2 1.2 1 0.8 0.6 0.4 0.2 0 01 34 6 5 input leak current : i li ( a) fig.21 input leakage current i li (a2,scl,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 1.2 1 0.8 0.6 0.4 0.2 0 01 34 6 5 output leak current : i lo ( a) fig.22 output leakage current i lo (sda) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 2.5 2 1.5 1 0.5 0 01 34 6 5 current consumption at writing : i cc 1 (ma) fig.23 write operating current i cc 1 (f scl = 400khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 400khz data = aah 2 0.6 0.5 0.4 0.3 0.2 0.1 0 01 34 6 5 current consumption at reading : i cc 2 (ma) fig.24 read operating current i cc 2 (f scl = 400khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl =400khz data=aah 2 2.5 2 1.5 1 0.5 0 01 34 6 5 current consumption at writing : i cc 1 (ma) fig.25 write operating current i cc 1 (f scl = 100khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 100khz data = aah
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 23/25 2 0.6 0.5 0.4 0.3 0.2 0.1 0 01 34 6 5 current consumption at reading : i cc 2 (ma) fig.26 read operating current i cc 2 (f scl = 100khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 100khz data = aah 2 2.5 2 1.5 1 0.5 0 01 34 6 5 standby current : i sb ( a) fig.27 standby current i sb supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 10000 1000 100 10 1 01 34 6 5 scl frequency : f scl (khz) fig.28 clock frequency f scl supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c 2 5 3 4 2 1 0 01 34 6 5 data clk h time : t high ( s) fig.29 data clock "h" period t high supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 6 5 data clk l time : t low ( s) fig.30 data clock "l" period t low supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 6 5 start condition hold time : t hd:sta ( s) fig.31 start condition hold time t hd:sta supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 6 3 4 5 2 1 0 01 34 6 5 start condition set up time : t su:sta ( s) fig.32 start condition setup time t su:sta supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 50 ? 50 0 ? 100 ? 150 ? 200 01 34 6 5 input data hold time : t hd:dat (ns) fig.33 input data hold time t hd:dat (high) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 50 ? 50 0 ? 100 ? 150 ? 200 01 34 6 5 input data hold time : t hd:dat (ns) fig.34 input data hold time t hd:dat (low) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 24/25 2 300 100 200 0 ? 100 ? 200 01 34 6 5 input data set up time : t su:dat (ns) fig.35 input data setup time t su:dat (high) supply voltage : v cc (v) spec2 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 300 100 200 0 ? 100 ? 200 01 34 6 5 input data set up time : t su:dat (ns) fig.36 input data setup time t su:dat (low) supply voltage : v cc (v) spec2 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 6 5 output data delay time : t pd ( s) fig.37 output data delay time t pd 0 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 6 5 output data delay time : t pd ( s) fig.38 output data delay time t pd 1 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 6 5 output data hold time : t dh ( s) fig.39 output data hold time t dh 0 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 6 5 output data hold time : t dh ( s) fig.40 output data hold time t dh 1 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 6 5 stop condition set up time : t su:sto ( s) fig.41 stop condition setup time t su:sto supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 6 5 bus open time before transmission : t buf ( s) fig.42 bus free time t buf supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 6 3 4 5 2 1 0 01 34 6 5 internal writing cycle time : t wr (ms) fig.43 write cycle time t wr supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
br24l08-w / br24l08f-w / br24l08fj-w memory ics br24l08fv-w / br24l08fvm-w 25/25 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 5 noise reduction effective time : t i (scl h) ( s) fig.44 noise spike width t i (scl h) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 5 noise reduction effective time : t i (scl l) ( s) fig.45 noise spike width t i (scl l) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 5 noise reduction effective time : t i (sda h) ( s) fig.46 noise spike width t i (sda h) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 5 noise reduction effective time : t i (sda l) ( s) fig.47 noise spike width t i (sda l) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 0.2 ? 0.4 ? 0.2 0 ? 0.6 01 34 6 5 wp set up time : t su:wp ( s) fig.48 wp setup time t su:wp supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 1.2 0.6 0.8 1 0.4 0.2 0 01 34 6 5 wp effective time : t high:wp ( s) fig.49 wp high period t high:wp supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
appendix appendix1-rev1.0 the products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document use silicon as a basic material. products listed in this document are no antiradiation design. about export control order in japan products described herein are the objects of controlled goods in annex 1 (item 16) of export trade control order in japan. in case of export from japan, please confirm if it applies to "objective" criteria or an "informed" (by miti clause) on the basis of "catch all controls for non-proliferation of weapons of mass destruction.

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